Cadence Palladium Hybrid
Integrates a transaction-level model of the CPU subsystem running on a Cadence Virtual System Platform (VSP) with register-transfer level (RTL) for the rest of the SoC running on the Palladium platform. The solution accomplishes this by using Cadence’s Software Integrator technology to provide cross-domain memory coherency. This solution enables the software to execute at virtual platform speeds (typically between 50 – 100MIPS) and interact with the RTL of the design. The Cadence Palladium Hybrid tool also maintains memory coherency between the RTL and virtual domains, delivering 60X improvement in OS boot and 10X improvement in post-boot software execution.
* Hardware and software debug capabilities available concurrently during runtime, allowing efficient debug of complex hardware/software interaction issues.
* Increased validation throughput results from combining early validation start, shorter software-driven test runtime, better hardware/software debug and increased number of concurrent users per emulator.
* Accelerated embedded software development occurs earlier in the design cycle